Hitherto, direct detection systems have been mainly used as known optical communication reception systems. For performing the ultrahigh speed optical communication, however, the digital coherent reception performed through local light oscillation and an analog digital converter (ADC) to resolve the lack of an optical signal noise ratio (OSNR) and a linear distortion occurring due to the wavelength dispersion or the like has become increasingly mainstream.
Since communications are performed with an ultrahigh speed, a small margin of hardware is provided to perform oversampling by using a sampling frequency of the ADC. Therefore, sampling should be performed at appropriate time to attain proper signal quality.
FIG. 1 illustrates an exemplary configuration provided to attain the digital coherent reception in a related art. According to the above-described exemplary configuration, minimal sampling is performed, that is to say, the sampling is performed twice per a single symbol. Further, a deviation from appropriate sampling is observed through a Gardner phase detector (PD) and the deviation is fed back to perform the sampling at appropriate time.
Quadrature phase shift keying (QPSK) modulation will be exemplarily described with reference to FIG. 1. Namely, a transmitted signal light and a local oscillation light generated through a local light oscillator 102 are transmitted to a 90°-optical hybrid unit 101 and optical output signals (signals i and q) having a phase difference of 90° therebetween are converted into electrical signals via individual photoelectric converters 103 and 104. The electrical signals are amplified through electronic amplifiers 107 and 108 via alternating current (AC) couplers 105 and 106, and are transmitted to an analog digital converter (ADC) 110.
The ADC 110 samples the signals that are transmitted from the electronic amplifiers 107 and 108 based on a signal obtained by internally doubling a clock (ADC REFCLK) transmitted from a voltage-controlled oscillator (VCO) 131 and digitizes the sampled signals. Further, the ADC 110 outputs a signal obtained by subjecting the clock (ADC REFCLK) transmitted from the VCO 131 to frequency division performed through a frequency divider 111 as a clock of a digital signal processor (DSP) 113.
The DSP 113 distributes and outputs digital signals of two systems (e.g., 6-bit parallel signals) in chorological order for each of the systems through the demultiplexer 114, where the digital signals correspond to the signals i and q that are transmitted from the ADC 110. For example, the upper half and the lower half of a signal output from the demultiplexer 114 correspond to the individual signal i and signal q. Further, digital signals (each of the digital signals is, for example, a 6-bit signal) are individually assigned to the output signals in time sequence. The time difference between adjacent output signals corresponds to the time difference between sampling intervals.
The signal output from the demultiplexer 114 is transmitted to a wavelength dispersion-compensator 115 for wavelength dispersion-compensation, and a signal output from the wavelength dispersion-compensator 115 is transmitted to a digital phase adjuster (PHA) 116 for digital phase adjusting. Then, a signal output from the digital PHA 116 is transmitted to an adaptive equalization-waveform distortion-compensator-and-demodulator 117 for waveform distortion-compensation and demodulation.
On the other hand, the signal output from the digital PHA 116 is transmitted to a Gardner phase detector 119 of a sampling phase-controller 118. FIG. 2 illustrates the signal-to-signal relationship for the Gardner phase detector 119 in the related art. The symbol Z−1 indicates a delay element of the symbol 1/2 and corresponds to the time difference between the adjacent outputs of the digital PHA 116 (illustrated in FIG. 1). For example, signal points a, b, and c that are defined in an element 1191 of the Gardner phase detector 119 individually correspond to signal points a, b, and c of the digital PHA 116 illustrated in FIG. 1. In FIG. 2, substantially the same calculation as done in the element 1191 is performed for the signals corresponding to the signals i and q in terms of time, and the sum total of the calculation results is calculated to output a phase signal.
Returning to FIG. 1, the signal output from the Gardner phase detector 119 is fed back to the digital PHA 116 as a phase adjusting amount (θ) via the filter 120, and the output signal is given as a control signal of the above-described VCO 131 via a selector 123, a loop filter 126, a digital analog converter (DAC) 129, and a low-pass filter 130 in sequence. Namely, the impact of high-speed jitter and/or fluctuations of local oscillation light are fed back to the digital PHA 116 including a finite impulse response (FIR) filter and is removed. Further, a deviation from low-speed sampling, such as a wander, is fed back to the clock itself of the ADC 110 through the VCO 131 and is removed. Consequently, the number of stages of the FIR filter is decreased.
When the clock of the ADC 110 and the internal clock of the DSP 113 are not frequency-synchronized with the clock of transferred data (LINE-side CLK), correction processor including the wavelength dispersion or the like is displaced. When the frequency synchronism is not attained, the value of a signal output from the Gardner phase detector 119 is reduced with reference to the actual phase. Namely, since the waveform is not shaped, the level of each of sampled data items becomes random so that the sampled data items counteract each other at the sum-total calculation time. Consequently, the value of the output signal of the Gardner phase detector 119 is reduced.
At the starting (boot-up) time, therefore, the clock of the DSP 113 is temporarily frequency-synchronized with a reference clock (external REFCLK) with a precision of, for example, ±20 ppm, the reference clock including a quartz oscillator or the like. After that, the synchronism is switched to the clock of transferred data (LINE-side CLK). In FIG. 1, the external reference clock-generator 112 corresponds to the above-described reference clock (external REFCLK) and performs the phase detection through the phase detector 121 in conjunction with a clock transmitted from the frequency divider 111 of the ADC 110. Then, at the starting time, the selector 123 is set on the phase detector 121-side so that a loop including the loop filter 126, the DAC 129, the low-pass filter 130, the VCO 131, the frequency divider 111, and the phase detector 121 is formed. Further, the clock of the DSP 113 is synchronized with the external REFCLK of the external reference clock-generator 112.
Since the transferred data itself disappears at the loss of signal (LOS) time during the normal operations, the switch-back to the reference clock (external REFCLK) is made. After the LOS is released, the switch to the clock of the transferred data (LINE-side CLK) is made.
Thus, during the digital coherent reception, the frequency synchronism with the reference clock (external REFCLK) is temporarily achieved at the starting time and the signal loss-time. After that, the switch to the clock of the transferred data (the LINE-side CLK) is made. However, what should be the trigger of making the switch is to be determined.
According to the known direct detection, the signal of direct current (DC) level-input light acquired from a signal light and/or that of alternating current (AC) level-input light acquired through the peak detector or the like is used as the above-described trigger. According to the known direct detection, the waveform is shaped on the transmission path. Therefore, the waveform had already been shaped at the reception device-input time so that a clock is generated based on the shaped waveform. Consequently, the clock is switched to the LINE-side at the time when an input signal is transmitted. When the switch-back to the reference clock is made due to the signal loss during the normal operations, an input waveform is also shaped at the time when an input signal is transmitted. Therefore, the clock may be reproduced in a relatively short time so that the recovery time is reduced even though the switch-back is made.
During the digital coherent reception, however, a clock toward the ADC affects not only sampling data but also various types of signal processor performed through the DSP, the signal processor including dispersion compensation or the like synchronized with the above-described clock. Consequently, the waveform is distorted, which makes it difficult to properly perform the phase detection. Therefore, when the switch to the LINE-side is made due to mere input, there is a possibility that the synchronism is delayed. Further, it may also become difficult to attain the pull-in. In that case, it may take a longer time to make the switch to the asynchronous-side again.
Further, there has been the technology of maintaining a clock frequency obtained immediately before the signal loss occurrence by maintaining the control voltage of the voltage-controlled oscillator (refer to Patent Document 2, for example). However, even though the above-described technology is used, the output frequency of the voltage-controlled oscillator fluctuates due to a temperature drift or the like so that the input waveform is not properly shaped. Consequently, it may become difficult to perform the phase detection and attain the LINE-side synchronism even though the signal loss is released.